Parts

Partname: Tentlabs XO3 pcb

Used to replace the internal clock of the CD-PRO2LF and to reduce the system clock jitter. The board is optional. It provides as well the option to reclock the EBU/Spdiff output and to generate as well an additional stable clock output to run an external DAC on if required. More….

In a CD system the bumps on the disc are read and converted into data for the DA converter. In this system one can have Jitter at the input side and Jitter at the output side.

Jitter is the fluctuation of the clock with respect to the signal (or the other way around) in the time domain.

Input side

Output side

CD-readout system for music

The bump or pits recorded onto the disc are read out by the CD system and result in signals of various length like the length of the pits on the picture. If one writes all these signals over each other on an oscilloscope it would theoretically look like the picture to the right.

In the diagram above the zero line is drawn.

Below this line the signal is considered to be a 0 and above the line it is a 1. At the decision moments determined by the clock of the data slicer the signal is judged. The clock strokes are green in the diagram.

In the picture of the bumps the size of the readout beam is as well indicated by the red circle. The beam is about 0.9 umeter and the track is about 0.6 umeter wide. This explains for the rise time of the edges in the eye pattern to the right.

Unfortunately the reality is not as beautiful as the theory. Because of the imperfect readout, jitter and noise occurs in the actual signal.

At the crossing point of the dark blue line ( decision level) and the green lines ( decision moment) the system looks at the level of the signal and labels it as 0 or 1. The larger the blue circle can be made the less room there is for error. A stable green clock is therefore most important in combination with low noise levels

At the output of the system in the digital domain the same happens. Therefore the X03 works double as it provides as well a system clock for the input side as a stable reclocked signal at the output side.

For implementation details see here….

VAU1254 CD-PRO2LF latest version